Type
Frequency range
Package Dimensions
Number of Inputs
Number of Outputs
Data Sheet
SiT92110
< 250 MHz
32-pin QFN, 5x5 mm
1 (LVPECL, LVDS, LVCMOS, SSTL, HCSL)
10 (Single Ended LVCMOS)
Frequency range
< 250 MHz
Package Dimensions
32-pin QFN, 5x5 mm
Number of Inputs
1 (LVPECL, LVDS, LVCMOS, SSTL, HCSL)
Number of Outputs
10 (Single Ended LVCMOS)
SiT92112
< 200 MHz
8-pin DFN, 2x2 mm
1 (LVCMOS)
2 (Single Ended LVCMOS)
Frequency range
< 200 MHz
Package Dimensions
8-pin DFN, 2x2 mm
Number of Inputs
1 (LVCMOS)
Number of Outputs
2 (Single Ended LVCMOS)
SiT92113
< 250 MHz
24-pin QFN, 4x4 mm
1 (LVPECL, LVDS, LVCMOS, SSTL, HCSL)
5 (Single Ended LVCMOS)
Frequency range
< 250 MHz
Package Dimensions
24-pin QFN, 4x4 mm
Number of Inputs
1 (LVPECL, LVDS, LVCMOS, SSTL, HCSL)
Number of Outputs
5 (Single Ended LVCMOS)
SiT92114
< 200 MHz
8-pin DFN, 2x2 mm
1 (LVCMOS)
4 (Single Ended LVCMOS)
Frequency range
< 200 MHz
Package Dimensions
8-pin DFN, 2x2 mm
Number of Inputs
1 (LVCMOS)
Number of Outputs
4 (Single Ended LVCMOS)
SiT92206
< 2.1 GHz
36-pin QFN, 6x6 mm
3 (LVPECL, LVDS, LVCMOS, SSTL, HCSL)
6 (Differential LVPECL, LVDS, HCSL, LVCMOS)
Frequency range
< 2.1 GHz
Package Dimensions
36-pin QFN, 6x6 mm
Number of Inputs
3 (LVPECL, LVDS, LVCMOS, SSTL, HCSL)
Number of Outputs
6 (Differential LVPECL, LVDS, HCSL, LVCMOS)
SiT92208
< 2.1 GHz
40-pin QFN, 6x6 mm
3 (LVPECL, LVDS, LVCMOS, SSTL, HCSL)
8 (Differential LVPECL, LVDS, HCSL, LVCMOS)
Frequency range
< 2.1 GHz
Package Dimensions
40-pin QFN, 6x6 mm
Number of Inputs
3 (LVPECL, LVDS, LVCMOS, SSTL, HCSL)
Number of Outputs
8 (Differential LVPECL, LVDS, HCSL, LVCMOS)
SiT92211
< 2.1 GHz
48-pin QFN, 7x7 mm
1 (LVPECL, LVDS, LVCMOS, HCSL)
10 (Differential LVPECL, LVDS, HCSL, LVCMOS)
Frequency range
< 2.1 GHz
Package Dimensions
48-pin QFN, 7x7 mm
Number of Inputs
1 (LVPECL, LVDS, LVCMOS, HCSL)
Number of Outputs
10 (Differential LVPECL, LVDS, HCSL, LVCMOS)
SiT92216
< 2.1 GHz
32-pin QFN, 5x5 mm
1 (LVPECL, LVDS, LVCMOS, HCSL)
4 (Differential LVPECL, LVDS, HCSL, LVCMOS), 1 (Single Ended LVCMOS)
Frequency range
< 2.1 GHz
Package Dimensions
32-pin QFN, 5x5 mm
Number of Inputs
1 (LVPECL, LVDS, LVCMOS, HCSL)
Number of Outputs
4 (Differential LVPECL, LVDS, HCSL, LVCMOS), 1 (Single Ended LVCMOS)
High-performance LVCMOS or/and Differential fanout clock buffer with low additive phase jitter of only 50 fs RMS and up to 10 outputs. Different synchronous glitch-free output enable (OE) function to eliminate potential intermediate incorrect output clock cycles when enabling or disabling outputs. Products are available from a 1.8 V to 3.3 V supply voltage.
For some products the output drivers of each bank can be independently programmed to LVPECL, LVDS, HCSL or HIZ mode. The LVCMOS clock output.
The low-jitter fanout clock buffer family supports frequencies up to 2.1 GHz. It is ideal for low-jitter, high-frequency clock/data distribution and level translation applications.
High-Performance Buffers
- Fanout clock buffers for low jitter, high frequency clock/data distribution
- Output frequency up to 2.1 GHz
- Ultra-low output-to-output skew, as low as 30 ps (typical)
- Low additive jitter, 50 fs to 55 fs rms
- Low propagation delay, as low as < 1 .6 ns
- Output enable (OE) signal for output synchronization
- Level translation
Additional services
- Technical support by our engineers
- Free samples on request
